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| INTEGRATED CIRCUITS DATA SHEET TZA3017HW 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Product specification Supersedes data of 2002 Jan 16 2003 May 14 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter FEATURES * Single 3.3 V power supply * I2C-bus and pin programmable fibre optic transmitter. Synthesizer features * Supports SDH/SONET bit rates at 155.52, 622.08, 2488.32 and 2666.06 Mbits/s (STM16/OC48 + FEC) * Supports Gigabit Ethernet at 1250 and 3125 Mbits/s * Supports Fibre Channel at 1062.5 and 2125 Mbits/s * Loss Of Lock (LOL) indicator * ITU-T compliant jitter generation. Multiplexer features * 16:1, 10:1, 8:1 or 4:1 multiplexing ratio * Rail-to-rail parallel inputs compliant with LVPECL, CML and LVDS * 4-stage FIFO for wide tolerance to clock skew * Supports co-directional and contra-directional clocking * Programmable parity checking * CML data and clock outputs, and loop mode inputs * LVPECL outputs on parallel interface * Line loop back input * Diagnostic loop back output. Additional features with the I2C-bus GENERAL DESCRIPTION TZA3017HW * Exchangeable pin designations of RF clock with data for all I/Os for optimum connectivity * Reversible pin designations of parallel data bus bits for optimum connectivity * Four reference frequency ranges. APPLICATIONS * Any optical transmission system with bit rates between 30 Mbits/s and 3.2 Gbits/s * Physical interface IC in transmit channels * Transponder applications * Dense Wavelength Division Multiplexing (DWDM) systems. The TZA3017HW is a fully integrated optical network transmitter, containing a clock synthesizer and a multiplexer with multiplexing ratios of 16:1, 10:1, 8:1 or 4:1. The A-rate feature allows the IC to operate at any bit rate between 30 Mbits/s and 3.2 Gbits/s using a single reference frequency. The transmitter supports loop modes with serial clock and data inputs and outputs. All clock signals are generated using a fractional N synthesizer with 10 Hz resolution giving a true, continuous rate operation. For full configuration flexibility, the transmitter is programmable either by pin or via the I2C-bus. * A-rateTM(1) supports any bit rate from 30 Mbits/s to 3.2 Gbits/s with one reference frequency * Programmable frequency resolution of 10 Hz * Adjustable swings of data and clock outputs * CML outputs on parallel interface * Programmable polarity of all RF I/Os (1) Koninklijke Philips Electronics N.V. ORDERING INFORMATION TYPE NUMBER TZA3017HW PACKAGE NAME HTQFP100 DESCRIPTION plastic, heatsink thin quad flat package; 100 leads; body 14 x 14 x 1.0 mm VERSION SOT638-1 2003 May 14 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 May 14 2003 May 14 OVERFLOW FIFORESET PARERR PARERRQ PAREVEN PARITY PARITYQ D00 to D15 55 56 74 73 44 38 37 16 4, 6, 8, 10, 12, 15, 17, 19, 21, 23, 28, 30, 32, 95, 97, 99 D00Q to D15Q 16 3, 5, 7, 9, 11, 14, 16, 18, 20, 22, 27, 29, 31, 94, 96, 98 PICLK PICLKQ 35 34 W R PARITY CHECKER AND BUS SWAP 16 16 D C 2 67 66 60 4 deep FIFO 16 16 MUX 4:1 8:1 10 : 1 16 : 1 2 2 2 D C 2 89 88 92 91 85 86 52 2 CLKDIR POCLK POCLKQ 71 40 39 0 / 90 PHASE SHIFT 2 1, 25, 33, 36, 41, 49, 58, 61, 64, 65, 68, 77, 80, 83, 87, 90, 93, 100 57 48 47 43 42 18 MD0 MD1 PRSCLO LOL CREF VCCD VCCA VCCO VDD 75 69 51 2 CLOCK SYNTHESIZER POWER-ON RESET I2C-BUS 53 54 72 DLOOP DLOOPQ CLOOP CLOOPQ ENLOUTQ ENLINQ SCL(DR2) SDA(DR1) CS(DR0) UI 59 BLOCK DIAGRAM Philips Semiconductors handbook, full pagewidth 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter A-rateTM fibre optic transmitter MUXR1 MUXR0 46 CINQ 45 CIN DINQ 82 DIN 81 78 79 INTERRUPT CONTROLLER 84 INT DOUT DOUTQ COUT COUTQ 3 3 2 TZA3017HW 62 63 2, 13, 24, 26, 50, 70, 76 7 VEE MGW559 TZA3017HW TZA3017HW Product specification PRSCLOQ CREFQ Fig.1 Simplified block diagram. Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter PINNING SYMBOL VEE VCCD VEE D12Q D12 D11Q D11 D10Q D10 D09Q D09 D08Q D08 VEE D07Q D07 D06Q D06 D05Q D05 D04Q D04 D03Q D03 VEE VCCD VEE D02Q D02 D01Q D01 D00Q D00 VCCD PICLKQ PICLK VCCD PARITYQ PARITY POCLKQ 2003 May 14 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 DESCRIPTION supply voltage (digital part) ground parallel data input 12 inverted parallel data input 12 parallel data input 11 inverted parallel data input 11 parallel data input 10 inverted parallel data input 10 parallel data input 09 inverted parallel data input 09 parallel data input 08 inverted parallel data input 08 ground parallel data input 07 inverted parallel data input 07 parallel data input 06 inverted parallel data input 06 parallel data input 05 inverted parallel data input 05 parallel data input 04 inverted parallel data input 04 parallel data input 03 inverted parallel data input 03 ground supply voltage (digital part) ground parallel data input 02 inverted parallel data input 02 parallel data input 01 inverted parallel data input 01 parallel data input 00 inverted parallel data input 00 supply voltage (digital part) parallel clock input inverted parallel clock input supply voltage (digital part) parity input inverted parity input parallel clock output inverted 4 UI PARERRQ PARERR VCCA 72 73 74 75 VEE CLKDIR 70 71 CS(DR0) OVERFLOW FIFORESET LOL VCCD COUTQ COUT VCCD MD0 MD1 VCCD VCCD DOUTQ DOUT VCCD VCCO 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 SDA(DR1) 53 SYMBOL POCLK VCCD CREFQ CREF PAREVEN MUXR1 MUXR0 PRSCLOQ PRSCLO VCCD VEE VDD SCL(DR2) die pad common ground plane PIN 40 41 42 43 44 45 46 47 48 49 50 51 52 TZA3017HW DESCRIPTION parallel clock output supply voltage (digital part) reference clock input inverted reference clock input parity select (odd or even) multiplexing ratio select 1 multiplexing ratio select 0 prescaler output signal inverted prescaler output signal supply voltage (digital part) ground supply voltage (digital part) I2C-bus serial clock (data rate select 2) I2C-bus serial data (data rate select 1) chip select (data rate select 0) FIFO overflow alarm output FIFO reset input loss of lock output supply voltage (digital part) serial clock output inverted serial clock output supply voltage (digital part) parallel data input termination mode select 0 parallel data input termination mode select 1 supply voltage (digital part) supply voltage (digital part) serial data output inverted serial data output supply voltage (digital part) supply voltage (clock generator) ground selection between co- and contra-directional clocking user interface select parity error output inverted parity error output supply voltage (analog part) Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter SYMBOL VEE VCCD DINQ DIN VCCD CINQ CIN VCCD INT ENLOUTQ ENLINQ VCCD DLOOPQ DLOOP VCCD PIN 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 ground supply voltage (digital part) loop mode data input inverted loop mode data input supply voltage (digital part) loop mode clock input inverted loop mode clock input supply voltage (digital part) interrupt output diagnostic loop back enable input (active LOW) line loop back enable input (active LOW) supply voltage (digital part) loop mode data output inverted loop mode data output supply voltage (digital part) CLOOP VCCD D15Q D15 D14Q D14 D13Q D13 VCCD 92 93 94 95 96 97 98 99 100 DESCRIPTION SYMBOL CLOOPQ PIN 91 TZA3017HW DESCRIPTION loop mode clock output inverted loop mode clock output supply voltage (digital part) parallel data input 15 inverted parallel data input 15 parallel data input 14 inverted parallel data input 14 parallel data input 13 inverted parallel data input 13 supply voltage (digital part) 2003 May 14 5 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW 91 CLOOPQ 88 DLOOPQ handbook, full pagewidth 100 VCCD 99 D13 85 ENLOUTQ 86 ENLINQ 93 VCCD 92 CLOOP 90 VCCD 89 DLOOP 87 VCCD 83 VCCD 82 CIN 80 VCCD 79 DIN VCCD VEE D12Q D12 D11Q D11 D10Q D10 D09Q 77 VCCD 76 VEE 75 VCCA 74 PARERR 73 PARERRQ 72 UI 71 CLKDIR 70 VEE 69 VCCO 68 VCCD 67 DOUT 66 DOUTQ 65 VCCD 64 VCCD 63 MD1 62 MD0 61 VCCD 60 COUT 59 COUTQ 58 VCCD 57 LOL 56 FIFORESET 55 OVERFLOW 54 CS(DR0) 53 SDA(DR1) 52 SCL(DR2) 51 VDD VCCD 49 VEE 50 98 D13Q 96 D14Q 94 D15Q 81 CINQ 1 2 3 4 5 6 7 8 9 D09 10 D08Q 11 D08 12 VEE 13 D07Q 14 D07 15 D06Q 16 D06 17 D05Q 18 D05 19 D04Q 20 D04 21 D03Q 22 D03 23 VEE 24 VCCD 25 VEE 26 D02Q 27 D02 28 D01Q 29 D01 30 D00Q 31 D00 32 VCCD 33 PICLKQ 34 PICLK 35 VCCD 36 PARITYQ 37 PARITY 38 POCLKQ 39 POCLK 40 VCCD 41 CREFQ 42 CREF 43 PAREVEN 44 MUXR1 45 MUXR0 46 PRSCLOQ 47 PRSCLO 48 TZA3017HW 78 DINQ 97 D14 95 D15 84 INT MGW560 Fig.2 Pin configuration. 2003 May 14 6 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter FUNCTIONAL DESCRIPTION The TZA3017HW converts parallel input data into serial output data having a bit rate from 30 Mbits/s up to 3.2 Gbits/s. An internal clock synthesizer synchronizes the internal oscillator to an external reference frequency. The parallel input data is multiplexed at ratios of 16:1, 10:1, 8:1 or 4:1. Choice of user interface control The TZA3017HW can be controlled either via the I2C-bus or using programming pins DR0 to DR2. Pin UI selects the user interface required. I2C-bus control and A-rate functionality are enabled when pin UI is either open circuit or connected to VCC. Pre-programmed mode is enabled when pin UI is connected to VEE; see Table 1. Table 1 UI LOW HIGH Truth table for pin UI MODE pre-programmed I2C-bus control PIN 54 DR0 CS PIN 53 DR1 SDA PIN 52 DR2 SCL Table 3 TZA3017HW Truth table for selecting bit rate in pre-programmed mode (pin UI = VEE) DR1 LOW LOW HIGH HIGH LOW LOW HIGH HIGH DR0 LOW HIGH LOW HIGH LOW HIGH LOW HIGH PROTOCOL STM1/OC3 STM4/OC12 STM16/OC48 STM16 + FEC GE 10GE Fibre Channel Fibre Channel BIT RATE (Mbits/s) 155.52 622.08 2488.32 2666.06 1250.00 3125.00 1062.50 2125.00 DR2 LOW LOW LOW LOW HIGH HIGH HIGH HIGH After power-up, the TZA3017HW initiates a Power-On Reset (POR) sequence to restore the default settings of the I2C-bus registers, irrespective of the level on pin UI. The default settings are shown in Table 10. Clock synthesizer Refer to Fig.3. The clock synthesizer is a fractional N-type synthesizer which provides the A-rateTM functionality. It consists of a Voltage Controlled Oscillator (VCO), octave divider M, main divider N, fractional divider K, reference divider R, Phase Frequency Detector (PFD), integrated loop filter, Loss Of Lock (LOL) detection circuit, and a prescaler output buffer. The internal VCO is phase-locked to a reference clock signal of typically 19.44 MHz applied to pins CREF and CREFQ. The clock synthesizer has a 22-bit fractional N capability which allows any combination of bit rate and reference frequency between 18 x R and 21 x R MHz, where R is the reference division factor. The LSB (bit k[0]) of the fractional divider, should be set to logic 1 to avoid limit cycles. These are cycles of less than maximum length that generate spurs in the frequency spectrum. This leaves 21 bits (k[21:1]) available for programming the fraction, allowing a resolution frequency of approximately 10 Hz at a fixed reference frequency. The clock synthesizer does not require any external components, allowing easier application use. To comply with most transmission standards, the reference frequency must be very accurate with minimum phase noise in order to synthesize a pure RF clock signal that complies with the strictest requirements for jitter generation; see Section "Jitter performance". In I2C-bus control mode, the chip is configured using I2C-bus pins SDA and SCL. During I2C-bus read or write actions, pin CS must be HIGH. When pin CS is LOW, the programmed configuration remains active, but pins SDA and SCL are ignored. This allows several TZA3017HWs in the application with the same I2C-bus address to be selected separately. The I2C-bus address of the TZA3017HW is shown in Table 2. Table 2 A6 1 I2C-bus address of the TZA3017HW A5 0 A4 1 A3 0 A2 1 A1 0 A0 0 R/W X The function and content of the I2C-bus registers are described in Section "I2C-bus registers". Some functions in the TZA3017HW can be controlled either by the I2C-bus or a designated pin. The method required is specified by an extra bit named I2C 2003 May 14 7 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW handbook, full pagewidth REFERENCE DIVIDER R LOL up VCO OCTAVE DIVIDER CHARGE-PUMP AND LOOP FILTER MAIN DIVIDER M to MUX CREF CREFQ PHASEFREQUENCY DETECTOR down PRSCLO PRSCLOQ N 9 FRACTION CALCULATOR 9 22 MGW561 N[8:0] K[21:0] Fig.3 Block diagram of the clock synthesizer. Programming the reference clock Pre-programmed operation requires a reference clock frequency of between 18 and 21 MHz connected to pins CREF and CREFQ. However, to obtain the bit rates in Table 3, the reference clock frequency must be 19.44 MHz. For SDH/SONET applications, a reference clock frequency of 19.44 x R MHz is preferred. I2C-bus control operation allows any one of four possible reference clock frequency ranges to be selected by programming reference divider R using bits REFDIV in I2C-bus register SYNTHCNF (address B6H). The REFDIV bit settings, reference clock frequency ranges, and division factor are shown in Table 4. The reference frequency is always divided internally to the lowest range of 18 to 21 MHz. Table 4 Truth table for bits REFDIV in I2C-bus register SYNTHCNF R DIVISION FACTOR 1 2 4 8 SDH/SONET REFERENCE FREQUENCY (MHz) 19.44 38.88 77.76 155.52 REFERENCE FREQUENCY RANGE (MHz) 18 to 21 36 to 42 72 to 84 144 to 168 REFDIV 00 01 10 11 2003 May 14 8 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Programming the clock synthesizer The following dividers are used to program the clock synthesizer: the main divider N, the fractional divider K and the octave divider M. The division factor for M is obtained by first determining in which octave the desired bit rate belongs as shown in Figure 4 and Tables 5 and 6. Table 6 TZA3017HW Common optical transmission protocols and corresponding octaves BIT RATE (Mbits/s) 3125.00 2970.00 2666.06 2488.32 2380.00 2125.00 1485.00 1380.00 1300.00 1250.00 1062.50 1062.50 1062.50 622.08 595.00 425.00 265.63 212.50 200.00 155.52 125.00 125.00 106.25 51.84 OCTAVE 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 3 3 4 4 4 4 4 5 6 PROTOCOL 10GE 2xHDTV STM16/OC48 + FEC STM16/OC48 DV-6000 Fibre Channel 6 handbook, halfpage 5 4 3 2 1 0 HDTV D-1 Video DV-6010 Gigabit Ethernet (GE) Fibre Channel OptiConnect ISC STM4/OC12 DV-6400 Fibre Channel 28.125 56.25 112.5 225 450 900 1800 3600 MGT824 f (Mbits/s) Fig.4 Allocation of octaves for common bit rates shown on a logarithmic scale. OptiConnect Fibre Channel ESCON/SBCON STM1/OC3 FDDI Fast Ethernet Fibre Channel OC1 Table 5 Octave designation and M division factor HIGHEST BIT RATE (Mbits/s) 3200 1800 900 450 225 112.5 56.25 OCTAVE 0 1 2 3 4 5 6 M DIVISION FACTOR 1 2 4 8 16 32 64 LOWEST BIT RATE (Mbits/s) 1800 900 450 225 112.5 56.25 28.125 Once the octave and M division factor are known, the division factors for N and K can be calculated for a given reference frequency using the Flowchart in Fig.5. 2003 May 14 9 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW handbook, full pagewidth CALCULATE N and K n, k = bit rate x M x R f ref n is integer part k is fractional part yes k=0? no NILFRAC = 1 NILFRAC = 0 no no no 0.25 < k < 0.75 yes k 0.25 ? yes k 0.75 ? yes k = k + 0.5 N=2xn N=2xn N=2xn-1 k = k - 0.5 N=2xn+1 j = 21 k=kx2 no k1? yes Kj = 1 k=k-1 Kj = 0 decimal to binary conversion of fractional part j=j-1 j=0? yes Kj = 1 no Write K j into registers B3H, B4H and B5H Convert N to binary and write into registers B1H and B2H END MGW570 Fig.5 Flowchart for calculating N and K for the required bit rate. 2003 May 14 10 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter The following examples refer to the flowchart in Fig.5. TZA3017HW Example 1: An SDH or SONET link has a bit rate of 2488.32 Mbits/s (STM16/OC48) that corresponds to octave 0 and an M division factor of 1. If the reference frequency fref at pins CREF and CREFQ is 77.76 MHz, the division factor R is required to be 4. The initial values for integer n and fractional part k are calculated using the equation: 2488.32 Mbits x 1 x 4 bit rate x M x R n.k = --------------------------------------- = -------------------------------------------------------- = 128 77.76 MHz f ref In this example, n = 128 and k = 0. Since k is 0, fractional functionality is not required, so bit NILFRAC in I2C-bus register FRACN2 should be set to logic 1; see Table 19. N = n x 2 = 256 with no further correction required. The resulting values of R = 4, M = 1 and N = 256 are set by I2C-bus registers SYNTHCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17) and MAINDIV0 (Table 18). Example 2: An SDH or SONET link has a bit rate of 2666.057143 Mbits/s (15/14 x 2488.32 Mbits/s) (STM16/OC48 link with FEC) that corresponds to octave 0 and an M division factor of 1. If fref at pins CREF and CREFQ is 38.88 MHz, the division factor R is required to be 2. The values for n and k are calculated as follows: bit rate x M x R 2666.05714283 Mbits x 1 x 2 n.k = --------------------------------------- = ---------------------------------------------------------------------------- = 137.1428571 f ref 38.88 MHz In this example, n = 137 and k = 0.1428571. Fractional functionality is required, so bit NILFRAC in I2C-bus register FRACN2 should be set to logic 0. Since k is less than 0.25, k is corrected to k = k + 0.5 = 0.6428571, and N is corrected to N = n x 2 - 1 = 273. The resulting values of R = 2, M = 1, N = 273 and K = 10 1001 0010 0100 1001 0011 are set by I2C-bus registers SYNTHCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18), FRACN2 (Table 19), FRACN1 (Table 20) and FRACN0 (Table 21). The FEC bit rate is usually rounded up to 2666.06 Mbits/s, which actually gives a different value for k than in this example. Example 3: A Fibre Channel link has a bit rate of 1062.50 Mbits/s that corresponds to octave 1 and an M division factor of 2. If fref at pins CREF and CREFQ is 19.44 MHz, the division factor R is required to be 1. The values for n and k are 1062.50 Mbits x 2 x 1 bit rate x M x R calculated as follows: n.k = --------------------------------------- = -------------------------------------------------------- = 109.3106996 19.44 MHz f ref In this example, n = 109 and k = 0.3107. Fractional functionality is required, so bit NILFRAC in I2C-bus register FRACN2 should be set to logic 0. Since k is greater than 0.25 and less than 0.75, k does not need to be corrected. N is corrected to N = n x 2 = 218. The resulting values of R = 1, M = 2, N = 218 and K = 01 0011 1110 0010 1000 0001 are set by I2C-bus registers SYNTHCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18), FRACN2 (Table 19), FRACN1 (Table 20) and FRACN0 (Table 21). Example 4: A non standard transmission link has a bit rate of 3012 Mbits/s that corresponds to octave 0 and an M division factor of 1. If fref at pins CREF and CREFQ is 20.50 MHz, the division factor R is required to be 1. The values bit rate x M x R 3012 Mbits x 1 x 1 for n and k are calculated as follows: n.k = --------------------------------------- = ----------------------------------------------- = 146.9268293 f ref 20.50 MHz In this example, n = 146 and k = 0.9268293. Fractional functionality is required, so bit NILFRAC in I2C-bus register FRACN2 should be set to logic 0. Since k is greater than 0.75, k is corrected to k = k - 0.5 = 0.4268293, and N is corrected to N = n x 2 + 1 = 293. The resulting values of R = 1, M = 1, N = 293 and K = 01 1011 0101 0001 0010 1011 are set by I2C-bus registers SYNTHCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18), FRACN2 (Table 19), FRACN1 (Table 20) and FRACN0 (Table 21). If the I2C-bus is not used, the clock synthesizer can be set up for the eight pre-programmed bit rates shown in Table 3, by pins DR0, DR1 and DR2 using an external reference clock frequency of 19.44 MHz. 2003 May 14 11 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Prescaler outputs The frequency of prescaler outputs PRSCLO and PRSCLOQ is the VCO frequency divided by a ratio of N.K. If the synthesizer is in-lock, the frequency of the prescaler output is equal to the reference frequency at CREF and CREFQ divided by R. This provides an accurate reference that can be used by other phase locked loops in the application. If required, the polarity of the prescaler outputs can be inverted by setting bit PRSCLOINV in I2C-bus register IOCNF2. If no prescaler information is required, its output can be disabled by setting bit PRSCLOEN to logic 0 in the same register. In addition, the prescaler output can be set for type of output, termination mode and signal amplitude. These parameter settings also apply to the parallel clock outputs POCLK and POCLKQ and parity error outputs PARERR and PARERRQ. For programming details; see Section "Configuring the parallel interface". Loss of Lock (LOL) During normal operation, pin LOL should be LOW to indicate that the clock synthesizer is in-lock and that the output frequency corresponds to the programmed value. If pin LOL goes HIGH, phase and/or frequency lock is lost, and the output frequency may deviate from the programmed value. The LOL function is also available using I2C-bus registers INTERRUPT and STATUS; see Sections "Interrupt register" and "Status register". If bit LOL in register INTERRUPT is not masked, a loss of lock condition will generate an interrupt signal at pin INT. Bit LOL is masked by default; see Section "Interrupt generation". Jitter performance The clock synthesizer is optimized for minimum jitter generation. For all SDH/SONET bit rates, the generated jitter complies with ITU-T standard G.958 using a pure reference clock. To ensure negligible loss of performance, the reference signal should have a single sideband phase noise of better than -140 dBc/Hz, at frequencies of more than 12 kHz from the carrier. If reference divider R is used, this negative value is allowed to increase at approximately 20 x log (R). Reference input For optimum jitter performance and Power Supply Rejection Ratio (PSRR), the sensitive reference input should be driven differentially. If the reference frequency source (fref) is single-ended, the unused CREF or CREFQ input should be terminated with an impedance which TZA3017HW matches the source impedance Rsource; see Fig.6. The PSRR can be improved by AC coupling the reference frequency source to inputs CREF and CREFQ. Any low frequency noise injected from the fref power supply will be attenuated by the resulting high-pass filter. The low cut-off frequency of the AC coupling must be lower than the reference frequency, otherwise the reference signal will be attenuated and the signal to noise ratio will be made worse. The value of coupling capacitor C is calculated 1 using the formula: C > ---------------------------------2R source f ref handbook, halfpage VCCD VCC 50 50 CREF C CREFQ C Rsource Rsource fref on-chip off-chip MDB060 Fig.6 Reference input with single-ended clock source. Multiplexer The multiplexer comprises a high-speed input register, a 4-bit deep First In First Out (FIFO) elastic buffer, a parity check circuit and a multiplexing tree. Parallel data bus clocking schemes The TZA3017HW supports both co-directional and contra-directional clocking schemes for the parallel data bus; see Figs 7 and 8. The clocking scheme is selected by pin CLKDIR or I2C-bus bit CLKDIR in I2C-bus register MUXCNF1 (address A1H). Co-directional clocking is the default setting, and is selected when pin CLKDIR is HIGH or when I2C-bus bit CLKDIR is set to logic 1. With co-directional clocking selected, the incoming clock is applied to pins PICLK and PICLKQ and the input data is applied to pins D00 and D00Q to D15 and D15Q. A parallel output clock is also available, if required, at pins POCLK and POCLKQ, and can be disabled by bit POCLKEN in I2C-bus register MUXCNF1. 12 2003 May 14 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter When contra-directional clocking is selected, any incoming clock at pins PICLK and PICLKQ is not used. In contra-directional clocking mode, the incoming data on the parallel data bus is sampled by the internally generated parallel output clock. In this mode, the parallel data source must be clocked using the parallel output clock signal at pins POCLK and POCLKQ. To avoid timing problems, the clock signal at pins POCLK and POCLKQ can be phase shifted with respect to the internal clock in four 90 degree steps, controlled by bits POCLKINV and POPHASE in I2C-bus register MUXCNF1 (address A1H); see Table 7. Table 7 TZA3017HW Truth table for bits POCLKINV and POPHASE in I2C-bus register MUXCNF1 POPHASE 0 1 0 1 PHASE SHIFT 0 90 180 270 POCLKINV 0 0 1 1 handbook, full pagewidth FRAMER TZA3017HW PARITY PARITYQ 16 D00 to D15 D00Q to D15Q PICLK PICLKQ POCLK POCLKQ FIFORESET CREF MGW565 TX_PARITY TX_DATA 16 TX_CLK TX_CLK_SRC system clock Fig.7 Co-directional clocking. 2003 May 14 13 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW handbook, full pagewidth FRAMER TZA3017HW PARITY PARITYQ 16 D00 to D15 D00Q to D15Q TX_PARITY TX_DATA 16 TX_CLK_SRC POCLK POCLKQ FIFORESET CREF MGW566 system clock Fig.8 Contra-directional clocking. FIFO In the co-directional clocking scheme, the FIFO input register samples the incoming parallel data on the rising edge of the clock signal at pins PICLK and PICLKQ. Data is retrieved from the FIFO by an internal clock, derived from the multiplexing tree clock generator. This provides a high tolerance to jitter, or clock skew, at inputs on the parallel interface; the FIFO can compensate for brief phase deviations, or clock skew, of up to plus or minus 1 unit interval. Large phase deviations will most likely cause the FIFO to either overflow or underflow, and is indicated by bit OVERFLOW in both I2C-bus registers INTERRUPT and STATUS; see Sections "Interrupt register" and "Status register". A FIFO overflow is also indicated by a HIGH level at pin OVERFLOW. If bit OVERFLOW in register INTERRUPT is not masked, a FIFO overflow or underflow condition will generate an interrupt signal at pin INT; see Section "Interrupt generation". The overflow interrupt exists until the FIFO is reset by a HIGH level on pin FIFORESET or by setting bits FIFORESET and I2CFIFORESET in I2C-bus register MUXCNF0 (address A2H). FIFORESET also initializes the FIFO. For optimum performance, the FIFO should be reset whenever there has been a Loss Of Lock condition, or whenever the bit rate is changed. The FIFORESET signal is re-timed by the internal clock generator signal. The FIFO will initialize two clock cycles after FIFORESET goes HIGH and is operational two clock cycles after FIFORESET goes LOW. The FIFO can be initialized automatically when an overflow occurs by connecting pin OVERFLOW to pin FIFORESET. Adjustable multiplexing ratio For optimum layout connectivity, the physical positions of parallel data bus pins D00 and D00Q to D15 and D15Q on the chip are located either side of pin VEE (pin 13). The number of parallel data bus inputs that are used depends on the multiplexing ratio selected by pins MUXR0 and MUXR1 or by bits MUXR in I2C-bus register MUXCNF1 (address A1H). Any unused parallel data bus inputs are disabled. The configuration settings and active inputs for each multiplexing ratio are shown in Table 8. In I2C-bus control mode, the default multiplexing ratio is 16:1. For multiplexing ratios 16:1, 8:1 and 4:1, the MSB is transmitted first. For multiplexing ratio 10:1, the LSB is transmitted first. 2003 May 14 14 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW To allow optimum layout connectivity, the pin designations of the parallel data bus bits can be reversed so that the default designated pin for the MSB is exchanged with the default designated pin for the LSB. This is implemented by bit BUSSWAP in I2C-bus register MUXCNF2 (address A0H). The highest supported speed for the parallel data bus is 400 Mbits/s. Therefore a multiplexing ratio of 4:1 will support bit rates of up to 1.6 Gbits/s. Table 8 Setting multiplexing ratio PIN MUXR0 LOW HIGH LOW HIGH BITS MUX (REG. MUXCNF1) 00 01 10 11 MULTIPLEXING RATIO 4:1 8:1 10:1 16:1 ACTIVE INPUTS LSB to MSB D06 to D09 D04 to D11 D03 to D12 D00 to D15 PIN MUXR1 LOW LOW HIGH HIGH Parity checking The parity checking function verifies the integrity of the incoming data on the parallel data bus. The calculated parity is compared to the parity expected at pins PARITY and PARITYQ. If these levels do not match, a parity error has occurred and pin PARERR goes HIGH during the next parallel clock period at pins PICLK and PICLKQ; (see Fig.9). The calculated parity can be configured to be either odd or even by pin PAREVEN or by bit PARITY in I2C-bus register MUXCNF2 (address A0H). Odd parity is configured by either a LOW level at pin PAREVEN or setting bit PARITY. The default setting for bit PARITY is even parity (logic 0). handbook, full pagewidth PICLK D00-D15 PARITY PARERR PARITY ERROR MDB063 Fig.9 Parity timing. 2003 May 14 15 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Configuring the parallel interface There are several options for configuring the parallel interface which comprises the parallel data bus and associated inputs and outputs. The options for parallel clock outputs POCLK and POCLKQ, parity error outputs PARERR and PARERRQ and prescaler outputs PRSCLO and PRSCLOQ are: output driver type, termination mode and output amplitude. I2C-bus register IOCNF2, bit MFOUTMODE selects either the CML or LVPECL output driver. The default is LVPECL. Bit MFOUTTERM sets the output termination mode to either standard LVPECL or floating termination, or in CML mode, to either DC or AC-coupled. In all cases, bits MFS adjust the amplitude. The default output amplitude is 850 mV (p-p), single-ended. The signal polarity and selective enabling or disabling of POCLK, POCLKQ, PRSCLO and PRSCLOQ can also be configured. These options are set in I2C-bus registers MUXCNF1 (address A1H) and IOCNF2 (address C8H). TZA3017HW In I2C-bus register MUXCNF2 (address A0H), setting bit PDINV inverts the polarity of the parallel data. Setting bit PICLKINV inverts the co-directional input clock on pins PICLK and PICLKQ so that the clock edge is shifted by half a clock cycle, changing the rising edge to a falling edge. This function can be used to resolve a parallel data bus timing problem. Rail-to-rail parallel data and clock inputs The differential parallel data, parity and clock inputs, D00 to D15, D00Q to D15Q, PARITY, PARITYQ, PICLK, and PICLKQ can handle input swings from 100 mV, single-ended, to a maximum of 1000 mV. These rail-to-rail inputs can also accept any absolute value between VEE and VCC. To keep the number of external components required to a minimum, most of the common standards: LVPECL, CML and LVDS are terminated internally; see Fig.10. handbook, full pagewidth VCCD VCCD VCCD 2V D 50 D 50 D 50 50 DQ DQ 50 DQ 50 VEE Floating and LVDS termination VEE CML termination VEE LVPECL termination MDB062 Fig.10 Rail-to-rail input termination configurations. 2003 May 14 16 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter The termination mode is determined by pins MD0 and MD1; see Table 9. Table 9 Input termination mode selection PIN MD0 0 1 0 1 INPUT MODE floating LVDS CML LVPECL TERMINATION 100 differential 100 differential (hysteresis on) 50 to VCC 50 to VCC - 2 V TZA3017HW The default pin designations for RF output data and clock are exchanged by setting bit CDOUTSWAP in I2C-bus register IOCNF1 so that signals at pins COUT and COUTQ are treated as data and signals at pins DOUT and DOUTQ are treated as clock. The default pin designations for Loop mode output data and clock are exchanged by setting bit CDLOOPSWAP in I2C-bus register IOCNF0 (address CBH) so that loop mode output data is present at pins CLOOP and CLOOPQ and loop mode clock output is present at pins DLOOP and DLOOPQ. Outputs DOUT and DOUTQ and COUT and COUTQ can be independently disabled by bits DOUTENA and COUTENA in I2C-bus register IOCNF1 (address CAH). The amplitude of the RF serial output signals in CML drive mode, is adjustable (in 16 steps) between 70 mV (p-p) and 1100 mV (p-p), single-ended, controlled by bits RFS in I2C-bus register IOCNF0 (address CBH). The default amplitude is 280 mV (p-p), single-ended. The RF serial outputs can be either DC or AC-coupled, terminated by bit RFOUTTERM in I2C-bus register IOCNF0 (address CBH). The default termination is DC-coupled. CMOS control inputs CMOS control inputs UI, MUXR0, MUXR1, PAREVEN, CLKDIR, ENLOUTQ, ENLINQ, MD0, MD1, FIFORESET and CS(DR0) have an internal pull-up resistor so that these pins go HIGH when open circuit, and only go LOW when deliberately forced. This is also true for pins DR1 and DR2 in pre-programmed mode (pin UI is LOW). In I2C-bus control mode (pin UI is HIGH), pins SCL and SDA comply with the I2C-bus interface standard. Power supply connections Four separate supply domains (VDD, VCCD, VCCO and VCCA) provide isolation between the various functional blocks. Each supply domain should be connected to a common VCC using a separate filter. All supply pins, including the exposed die pad, must be connected. The die pad connection to ground must have the lowest possible inductance. Since the die pad is also used as the main ground return of the chip, this connection must also have a low DC impedance. The voltage supply levels should be in accordance with the values specified in Chapters "Characteristics" and "Limiting values". All external components should be surface mounted, with a preferable size of 0603 or smaller. The components must be mounted as close to the IC as possible. PIN MD1 0 0 1 1 The LVDS mode has a differential hysteresis of 30 mV implemented by default. Setting bit PIHYST in I2C-bus register MUXCNF0 (address A2H) activates hysteresis for all input modes. Loop mode I/Os In line loopback mode, the internal data and clock routing switch selects serial data and clock signals from inputs DIN, DINQ, CIN, and CINQ instead of from the output of the multiplexer. Line loopback mode is activated by a LOW level on pin ENLINQ. Line loopback mode is also selected by setting bit ENLIN in I2C-bus register MUXCNF2 (address A0H). In diagnostic loopback mode, the synthesized serial data and clock signals are available at loop mode output pins DLOOP and DLOOPQ, and CLOOP and CLOOPQ and at output pins DOUT and DOUTQ and COUT and COUTQ. Diagnostic loopback mode is activated by making pin ENLOUTQ LOW. Diagnostic loopback mode is also selected by setting bit ENLOUT in I2C-bus register MUXCNF2 (address A0H). Configuring the RF I/Os The polarity of specific RF serial data and clock I/O signals can be inverted using I2C-bus registers IOCNF0 (address CBH) and IOCNF1 (address CAH). To allow easier connection to other ICs, the pin designations for input data can be exchanged with the pin designations for input clock. The pin designations for output data and output clock can also be exchanged. The default pin designations for loop mode input data and clock are exchanged by setting bit CDINSWAP in I2C-bus register IOCNF1 so that signals at pins CIN and CINQ are treated as data and signals at pins DIN and DINQ are treated as clock. 2003 May 14 17 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Interrupt register The following events are recorded by setting the appropriate bit(s) in I2C-bus register INTERRUPT (address 00H): * Loss of lock * High junction temperature * FIFO overflow or underflow. When register INTERRUPT is polled by an I2C-bus read action, any set bits are reset. If a condition is still active, the corresponding bit remains set. Status register The current status of the conditions that are recorded by register INTERRUPT are indicated by setting the appropriate bit(s) in I2C-bus register STATUS (address 01H). A bit is set only for the period that the condition is active and resets when the condition clears. Register STATUS is polled by an I2C-bus read action. Interrupt generation An interrupt is generated if an interrupt condition sets a bit in I2C-bus register INTERRUPT (address 00H) and if the bit is not masked by I2C-bus register INTMASK (address CCH). Only the high junction temperature interrupt bit is not masked by default. A generated interrupt is indicated by an active logic level at pin INT. TZA3017HW The active output level used is set by bit INTPOL in I2C-bus register INTMASK. The default is an active LOW level. Bit INTOUT sets the output mode at pin INT to either open-drain or to standard CMOS. The default is open-drain. An active LOW output in open-drain mode allows several receivers to be connected together, and requires only one 3.3 k pull-up resistor. CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Bit transfer Refer to Fig.11. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed MBC621 Fig.11 Bit transfer. 2003 May 14 18 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Start and stop conditions TZA3017HW Refer to Fig.12. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). handbook, full pagewidth SDA SDA SCL S START condition P STOP condition SCL MBC622 Fig.12 Definition of start and stop conditions. System configuration Refer to Fig.13. A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER MBA605 SLAVE RECEIVER MASTER TRANSMITTER Fig.13 System configuration. 2003 May 14 19 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Acknowledge Refer to Fig.14. Only one data byte is transferred between the start and stop conditions during a write from the transmitter to the receiver. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. TZA3017HW The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition; see Fig.17. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement MBC602 1 2 8 9 Fig.14 Acknowledgment on the I2C-bus. 2003 May 14 20 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter I2C-BUS PROTOCOL Addressing TZA3017HW Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The address byte is sent after the start condition. The master transmitter/receiver either reads from the read-registers or writes to the write-registers. It is not possible to read from and write to the same register. Figure 15 shows how the slave and register address bytes are defined. handbook, full pagewidth MSB LSB MSB LSB R/W 1 Slave address Register address MDB070 Fig.15 Slave and register addresses. Read/Write protocols The protocol for writing to a single register is shown in Fig.16. The transmitter sends the address of the slave device, waits for an acknowledge from the slave, sends register address, waits for an acknowledge from the slave, sends data byte, waits for an acknowledge from the slave, followed by a stop condition. handbook, full pagewidth acknowledge from slave R/W MSB S SLAVE ADDRESS acknowledge from slave MSB REGISTER ADDRESS acknowledge from slave LSB 0A1 A DATA A P one byte transferred MDB386 Fig.16 Write protocol. 2003 May 14 21 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW The protocol for reading one or more registers is shown in Fig.17. The receiver sends the address of the slave device, waits for an acknowledge from the slave, receives data byte(s) from slave (the TZA3017AHW starts sending data after asserting an acknowledge), after receiving the data, the receiver sends an acknowledge or, if finished, a not-acknowledge, followed by a stop condition. handbook, full pagewidth acknowledge from slave R/W S SLAVE ADDRESS MSB acknowledge from master (1) LSB acknowledge from master (1) MSB acknowledge from master (1) LSB 1A DATA A A DATA A P first byte last byte MDB387 (1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. Fig.17 Read protocol. I2C-bus registers The I2C-bus registers are accessed in I2C-bus control mode by setting pin UI HIGH or leaving pin UI open circuit. Address and read/write data are transferred serially via pin SDA and clocked via pin SCL when pin CS (chip select) is HIGH. The I2C-bus registers are listed in Table 10. 2003 May 14 22 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Table 10 I2C-bus registers ADDRESS (HEX)(1) 00 01 A0 A1 A2 B0 B1 B2 B3 B4 B5 B6 C8 CA CB CC FD Note 1. Addresses not shown must not be accessed. Table 11 Register INTERRUPT (address 00H) BIT 7 6 5 4 3 2 1 0 1 0 X 1 0 1 0 0 0 X X PARAMETER DESCRIPTION clock synthesizer Loss of Lock (LOL) out of lock (loss of lock condition) in lock reserved high junction temperature junction temperature 130 C junction temperature < 130 C FIFO overflow or underflow overflow or underflow normal operation reserved NAME INTERRUPT STATUS MUXCNF2 MUXCNF1 MUXCNF0 DIVCNF MAINDIV1 MAINDIV0 FRACN2 FRACN1 FRACN0 SYNTHCNF IOCNF2 IOCNF1 IOCNF0 INTMASK MUXTIMING FUNCTION Interrupt register; see Table 11 Status register; see Table 12 Multiplexer configuration register 2; see Table 13 Multiplexer configuration register 1; see Table 14 Multiplexer configuration register 0; see Table 15 Octave and loop mode configuration register; see Table 16 Main divider division factor N; most significant byte; range 128 to 511; see Table 17 Fractional divider division factor K; see Table 19 Fractional divider division factor K; see Table 20 Fractional divider division factor K; see Table 21 Clock synthesizer configuration register; see Table 22 Parallel interface output configuration register 2; see Table 23 RF serial I/O configuration register 1; see Table 24 RF serial output configuration register 0; see Table 25 Interrupt masking register; see Table 26 Multiplexer timing register; see Table 27 TZA3017HW DEFAULT VALUE - - 0000 0000 0110 1001 0001 1000 0000 0000 0000 0001 READ/ WRITE R R W W W W W W W W W W W W W W W Main divider division factor N; least significant byte; see Table 18 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0010 1100 1100 0000 0000 0011 0101 0000 0000 1000 NAME LOL TALARM OVERFLOW 2003 May 14 23 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Table 12 Register STATUS (address 01H) BIT 7 6 5 4 3 2 1 0 1 0 X 1 0 1 0 0 0 X X PARAMETER DESCRIPTION clock synthesizer Loss of Lock (LOL) out of lock (loss of lock condition) in lock reserved high junction temperature junction temperature 130 C junction temperature < 130 C FIFO overflow or underflow overflow or underflow normal operation reserved TZA3017HW NAME LOL TALARM OVERFLOW 2003 May 14 24 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Table 13 Register MUXCNF2 (address A0H); default value 00H BIT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 PARAMETER DESCRIPTION parallel data bus bit designations D00 = MSB, D15 = LSB (reversed) D15 = MSB, D00 = LSB (normal) parity checking odd parity even parity parity programming via I2C-bus interface via pin PAREVEN parallel clock input polarity inverted normal parallel data input polarity inverted normal enable/disable loop mode inputs enabled disabled enable/disable loop mode outputs enabled disabled loop mode control via I2C-bus interface via pins ENLINQ and/or ENLOUTQ default value TZA3017HW NAME BUSSWAP PARITY I2CPARITY PICLKINV PDINV ENLIN ENLOUT I2CLOOPMODE 2003 May 14 25 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Table 14 Register MUXCNF1 (address A1H); default value 69H BIT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 enabled disabled parallel clock output phase 90 phase shift 0 phase shift parallel clock output polarity inverted normal parallel clock direction co-directional contra-directional parallel clock direction programming via I2C-bus interface via pin CLKDIR multiplexing ratio 16:1 10:1 8:1 4:1 multiplexing ratio programming via I2C-bus interface via pins MUXR0 and MUXR1 default value PARAMETER DESCRIPTION parallel clock output enable TZA3017HW NAME POCLKEN POPHASE POCLKINV CLKDIR I2CLKDIR MUXR I2CMUXR 2003 May 14 26 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Table 15 Register MUXCNF0 (address A2H); default value 18H BIT 7 6 5 4 3 2 1 0 FIFO reset 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 reset normal mode FIFO reset programming via I2C-bus interface via pin FIFORESET parallel input hysteresis all input modes LVDS mode only reserved default value PARAMETER DESCRIPTION TZA3017HW NAME FIFORESET I2CFIFORESET PIHYST Table 16 Register DIVCNF (address B0H); default value 00H BIT 7 6 5 4 3 2 1 0 PARAMETER DESCRIPTION octave divider division factor M, octave selection 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 M = 1, octave number 0 M = 2, octave number 1 M = 4, octave number 2 M = 8, octave number 3 M = 16, octave number 4 M = 32, octave number 5 M = 64, octave number 6 reserved default value DIV_M NAME Table 17 Register MAINDIV1 (address B1H); default value 01H BIT 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 N8 1 default value PARAMETER DESCRIPTION main divider division factor N; N8 = MSB DIV_N NAME Table 18 Register MAINDIV0 (address B2H); default value 00H BIT 7 N7 0 6 N6 0 5 N5 0 4 N4 0 3 N3 0 2 N2 0 1 N1 0 0 N0 0 default value 27 PARAMETER DESCRIPTION main divider division factor N; N0 = LSB DIV_N NAME 2003 May 14 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Table 19 Register FRACN2 (address B3H); default value 80H BIT 7 6 X 5 K21 4 K20 3 K19 2 K18 1 K17 0 PARAMETER DESCRIPTION TZA3017HW NAME DIV_K NILFRAC K16 fractional divider division value K; K21 = MSB NILFRAC control bit no fractional N functionality fractional N functionality 1 0 1 0 0 0 0 0 0 0 default value Table 20 Register FRACN1 (address B4H); default value 00H BIT 7 K15 0 6 K14 0 5 K13 0 4 K12 0 3 K11 0 2 K10 0 1 K9 0 0 K8 0 default value PARAMETER DESCRIPTION fractional divider division value K DIV_K NAME Table 21 Register FRACN0 (address B5H); default value 00H BIT 7 K7 0 6 K6 0 5 K5 0 4 K4 0 3 K3 0 2 K2 0 1 K1 0 0 K0 0 PARAMETER DESCRIPTION fractional divider division value K; K0 = LSB default value DIV_K NAME Table 22 Register SYNTHCNF (address B6H); default value 00H BIT 7 6 5 4 0 1 0 3 0 2 0 1 0 0 0 reserved clock synthesizer manual initialization toggle to initialize synthesizer normal operation; auto initialize reference divider division factor R; reference frequency 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 R = 8; 155.52 MHz R = 4; 77.76 MHz R = 2; 38.88 MHz R = 1; 19.44 MHz default value REFDIV INITSYNTH PARAMETER DESCRIPTION NAME 2003 May 14 28 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Table 23 Register IOCNF2 (address C8H); default value 2CH BIT 7 6 5 4 3 0 1 1 1 0 1 0 1 0 2 0 1 1 1 0 0 1 0 0 0 1 PARAMETER DESCRIPTION parallel output signal amplitude minimum: 60 mV (p-p) default: 850 mV (p-p) maximum: 1000 mV (p-p) prescaler output polarity inverted normal prescaler output enable enabled disabled parallel output termination LVPECL mode: floating; CML mode: AC-coupled LVPECL mode: standard; CML mode: DC-coupled parallel output mode 1 0 0 0 1 0 1 1 0 0 Current Mode Logic (CML) Low Voltage Positive Emitter Coupled Logic (LVPECL) default value TZA3017HW NAME MFS PRSCLOINV PRSCLOEN MFOUTTERM MFOUTMODE 2003 May 14 29 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Table 24 Register IOCNF1 (address CAH); default value C0H BIT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 inverted normal loop mode data input polarity inverted normal loop mode clock and data inputs swap clock and data input pairs swapped normal clock output polarity inverted normal data output polarity inverted normal clock and data outputs swap clock and data output pairs swapped normal serial clock output enable enabled disabled serial data output enable enabled disabled default value PARAMETER DESCRIPTION loop mode clock input polarity TZA3017HW NAME CININV DININV CDINSWAP COUTINV DOUTINV CDOUTSWAP COUTENA DOUTENA 2003 May 14 30 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Table 25 Register IOCNF0 (address CBH); default value 03H BIT 7 6 5 4 3 0 0 1 1 0 1 0 1 0 1 0 0 2 0 0 1 1 0 1 1 0 0 1 1 PARAMETER DESCRIPTION RF serial output signal amplitude minimum: 70 mV (p-p) default: 280 mV (p-p) maximum: 1100 mV (p-p) loop mode clock output polarity inverted normal loop mode data output polarity inverted normal RF serial output termination AC-coupled DC-coupled loop mode clock and data outputs swap clock and data output pairs swapped normal default value TZA3017HW NAME RFS CLOOPINV DLOOPINV RFOUTTERM CDLOOPSWAP 0 0 0 0 0 1 1 Table 26 Register INTMASK (address CCH); default value 50H BIT 7 6 5 4 3 2 1 0 1 0 0 0 0 PARAMETER DESCRIPTION mask LOL interrupt bit not masked masked; note 1 reserved mask high junction temperature interrupt bit not masked masked; note 1 mask OVERFLOW interrupt bit not masked masked; note 1 pin INT output polarity inverted; active LOW output normal; active HIGH output pin INT output mode standard CMOS output open-drain output default value MLOL NAME MTALARM 1 0 1 0 1 0 1 0 0 Note 1. Signal is not processed by interrupt controller. 2003 May 14 MOVERFLOW INTPOL INTOUT 1 0 1 0 0 0 0 31 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Table 27 Register MUXTIMING (address FDH); default value 80H BIT 7 0 0 0 6 0 0 0 5 0 0 0 4 0 0 0 3 0 1 1 2 1 0 0 1 0 0 0 0 0 0 0 PARAMETER DESCRIPTION multiplexing ratio 10:1 maximum bit rate up to 3.2 Gbits/s up to 2.7 Gbits/s default value TZA3017HW NAME MUX_TIMING TZA3017HW FEATURES IN PRE-PROGRAMMED MODE Although the TZA3017HW is primarily intended to be programmed via the I2C-bus, many of the TZA3017HW functions can be accessed either via the I2C-bus in I2C-bus control mode (pin UI HIGH), or via the external chip pins in pre-programmed mode (pin UI LOW). The TZA3017HW functions that are accessible in pre-programmed mode and their control pins are as follows: * Choice of four pre-programmed SDH/SONET bit rates: STM1/OC3, STM4/OC12, STM16/OC48, STM16/OC48 + FEC; pins DR0 to DR2 * Choice of four pre-programmed bit rates: Fibre Channel, double Fibre Channel, Gigabit Ethernet, 10-Gigabit Ethernet; pins DR0 to DR2 * Choice of four multiplexing ratios: 16:1, 10:1, 8:1 or 4:1: pins MUXR1 and MUXR0 * Co-directional or contra-directional clocking scheme: pin CLKDIR * Loop mode serial input and output configuration: pins ENLINQ and ENLOUTQ * Even/odd parity checking: pin PAREVEN * LVPECL outputs on parallel interface with 800 mV (p-p), single-ended signal, (DC-coupled termination to VCC - 2 V) * CML serial RF outputs with typical 280 mV (p-p), single-ended signal, (DC-coupled load) * Loss Of Lock indication (LOL) * FIFO overflow indication * FIFO reset * High junction temperature indication (pin INT; open-drain) * 18 to 21 MHz reference frequency supported. 2003 May 14 32 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCCD, VCCA, supply voltages VCCO,VDD Vn DC voltage on pins D00 to D15, D00Q to D15Q, PICLK, PICLKQ, PARITY, and PARITYQ POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO, and PRSCLOQ UI, CS, SDA, SCL, MUXR0, MUXR1, CLKDIR, PAREVEN, FIFORESET, MD0, MD1, ENLOUTQ and ENLINQ LOL and OVERFLOW INT In input current on pins D00 to D15, D00Q to D15Q, PICLK, PICLKQ, PARITY, and PARITYQ CREF, CREFQ, CIN, CINQ, DIN and DINQ INT Tamb Tj Tstg ambient temperature junction temperature storage temperature -65 -25 -20 -2 -40 VCC - 0.5 VCC - 2.5 -0.5 -0.5 -0.5 PARAMETER MIN. -0.5 TZA3017HW MAX. +3.6 V UNIT VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 +25 +20 +2 +85 +125 +150 V V V V V mA mA mA C C C THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Notes 1. In compliance with JEDEC standards JESD51-5 and JESD51-7. 2. Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and fourth layer in the PCB. PARAMETER thermal resistance from junction to ambient CONDITIONS notes 1 and 2 VALUE 16 UNIT K/W 2003 May 14 33 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW CHARACTERISTICS VCC = 3.14 to 3.47 V; Tamb = -40 to +85 C; Rth(j-a) 16 K/W; all characteristics are specified for the default settings (note 1); all voltages are referenced to ground; positive currents flow into the device unless otherwise specified. SYMBOL Supplies ICCA ICCD IDD ICCO ICC(tot) Ptot analog supply current digital supply current digital supply current oscillator supply current total supply current total power dissipation notes 1 and 2 notes 2 and 3 notes 1 and 2 notes 2 and 3 notes 1 and 2 notes 2 and 3 0.5 170 285 0 20 190 305 0.6 0.96 1.2 215 345 2 31 250 380 0.82 1.25 2.4 270 430 4 41 318 478 1.1 1.66 mA mA mA mA mA mA mA W W PARAMETER CONDITIONS MIN TYP MAX UNIT CMOS input; pins UI, DR0, DR1, DR2, MUXR0, MUXR1, MD0, MD1, ENLINQ, ENLOUTQ, FIFORESET, PAREVEN and CLKDIR VIL VIH IIL IIH VOL VOH VOL IOH Vo(p-p) Zo tr tf tD-C fSBR LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current VIL = 0 V VIH = VCC IOL = 1 mA IOH = -0.5 mA IOL = 1 mA VOH = VCC - 0.8VCC -200 - 0 VCC - 0.2 0 - 220 40 - - -50 40 30 30 - - - - - - - - 280 50 60 60 - 50 - - - - 0.2VCC - - 10 V V A A V V CMOS output; pins OVERFLOW, LOL and INT LOW-level output voltage HIGH-level output voltage 0.2 VCC 0.2 10 Open-drain output; pin INT LOW-level output voltage HIGH-level output current V A mV ps ps ps % Mbits/s Mbits/s Serial output; pins COUT, COUTQ, DOUT, DOUTQ, CLOOP, CLOOPQ, DLOOP, and DLOOPQ default output voltage swing single-ended with 50 (peak-to-peak value) external load; note 4 output impedance rise time fall time data-to-clock delay duty cycle COUT and COUTQ serial bit rate single-ended to VCC 20% to 80% 80% to 20% between differential crossovers between differential crossovers MUX 16:1, 8:1, 4:1 MUX 10:1; note 5 Serial input; pins DIN, DINQ, CIN and CINQ Vi(p-p) Vi 2003 May 14 input voltage (peak-to-peak value) input voltage range 34 single-ended 50 VCC - 1 1000 mV 340 60 90 90 50 60 3200 3200 VCC + 0.25 V Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter SYMBOL Zi Vi Vi(p-p) Vhys Zi(diff) Zi(se) VT(CML) VT(LVPECL) tsu(co) th(co) tsu(contra) th(contra) fPBR Vo(p-p) PARAMETER input impedance CONDITIONS single-ended to VCC 40 MIN 50 TYP TZA3017HW MAX 60 UNIT Parallel input (rail-to-rail); pins D00 to D15, D00Q to D15Q, PARITY, PARITYQ, PICLK, and PICLKQ input voltage range input voltage swing (peak-to-peak value) input differential hysteresis single-ended input impedance input termination voltage in CML mode input termination voltage in LVPECL mode set-up time hold time set-up time hold time duty cycle PICLK and PICLKQ parallel bit rate default output voltage swing single-ended with 50 (peak-to-peak value) external load, DC-coupled; note 6 output impedance rise time fall time single-ended to VCC 20% to 80% 80% to 20% 50 termination to VCC - 2V 50 termination to VCC - 2V single-ended MD1 = LOW; MD0 = HIGH MD1 = HIGH MD1 = HIGH; MD0 = LOW MD1 = HIGH; MD0 = HIGH co-directional clocking co-directional clocking contra-directional clocking contra-directional clocking between differential crossovers VEE - 0.25 - 100 - 80 40 - VCC - 2.3 0 1000 1300 -300 40 - 600 - 30 100 50 VCC VCC - 2 - - - - 50 - 850 VCC + 0.25 V 1000 - 120 60 - VCC - 1.7 - - - - 60 400 mV mV V V ps ps ps ps % Mbits/s differential input impedance MD1 = LOW CML mode output; pins POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO, and PRSCLOQ 1100 mV Zo tr tf VOH VOL Vo(p-p) 80 200 200 VCC - 1.2 VCC - 2.0 700 95 250 250 110 350 350 ps ps LVPECL mode output; pins POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO, and PRSCLOQ HIGH-level output voltage LOW-level output voltage VCC - 1.0 VCC - 0.9 VCC - 1.9 VCC - 1.7 900 1150 V V mV default output voltage swing LVPECL floating; (peak-to-peak value) single-ended with 50 external load rise time fall time 20% to 80% 80% to 20% tr tf Vi(p-p) Vi Zi 2003 May 14 300 300 350 350 - - 50 400 400 ps ps Reference frequency input; pins CREF, and CREFQ input voltage (peak-to-peak value) input voltage range input impedance single-ended to VCC 35 single-ended 50 VCC - 1 40 1000 mV VCC + 0.25 V 60 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter SYMBOL fCREF fCREF PARAMETER reference clock frequency accuracy reference clock frequency CONDITIONS SDH/SONET requirement see Table 4; R = 1, 2, 4, or 8 MIN -20 18 x R - TYP TZA3017HW MAX +20 UNIT ppm MHz 19.44 x R 21 x R I2C-bus; pins SCL and SDA VIL VIH Vhys VOL IL Ci LOW-level input voltage HIGH-level input voltage hysteresis of Schmitt trigger inputs SDA LOW-level output voltage (open-drain) input leakage current input capacitance IOL = 3 mA - 0.8VCC 0.05VCC 0 -10 - - 1.3 0.6 0.6 0.6 0 100 0.6 20 20 1.3 - 0 0.1VCC 0.2VCC - - - - - - - - - - - - - - - - - - - - - 0.2VCC - - 0.4 +10 10 V V V V A pF I2C-bus timing fSCL tLOW tHIGH tHD;STA tSU;STA tHD;DAT tSU;DAT tSU;STO tr tf tBUF Cb tSP VnL VnH SCL clock frequency SCL LOW time SCL HIGH time hold time START condition set-up time START condition data hold time data set-up time set-up time STOP condition SCL and SDA rise time SCL and SDA fall time bus free time between STOP and START capacitive load on each bus line pulse width of allowable spikes noise margin at LOW-level noise margin at HIGH-level 100 - - - - 0.9 - - 300 300 - 400 50 - - kHz s s s s s ns s ns ns s pF ns V V 2003 May 14 36 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter SYMBOL Jitter generation Jgen(p-p) jitter generation (peak-to-peak value) STM1/OC3 mode; notes 7 and 8 f = 500 Hz to 1.3 MHz f = 12 kHz to 1.3 MHz f = 65 kHz to 1.3 MHz STM4/OC12 mode; notes 7 and 8 f = 1 kHz to 5 MHz f = 12 kHz to 5 MHz f = 250 kHz to 5 MHz STM16/OC48 mode; notes 7 and 8 f = 5 kHz to 20 MHz f = 12 kHz to 20 MHz f = 1 MHz to 20 MHz Notes - - - 35 32 7 - - - - - - - - - - - - PARAMETER CONDITIONS MIN TYP TZA3017HW MAX UNIT 16 4 4 mUI mUI mUI 63 13 13 mUI mUI mUI 250 50 50 mUI mUI mUI 1. Default settings: UI = LOW (pre-programmed mode; see Table 1); DR0 = LOW, DR1 = HIGH, DR2 = LOW (STM16/OC48); PAREVEN = HIGH (even parity); MUXR0 = HIGH, MUXR1 = HIGH (multiplexing ratio is 16:1); FIFORESET = LOW; MD0 = LOW, MD1 = LOW (100 differential); CLKDIR = HIGH (co-directional clocking); ENLOUTQ = HIGH (DLOOP, DLOOPQ, CLOOP and CLOOPQ disabled); ENLINQ = HIGH (DIN, DINQ, CIN and CINQ disabled); CREF and CREFQ = 19.44MHz; COUT, COUTQ, DOUT, DOUTQ, POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO and PRSCLOQ are not connected. 2. The total supply current and power dissipation is dependent on the I2C settings such as output swing, loop modes, multiplexing ratio and input and output termination conditions. For dependency on output termination and output swing; see Figs 18 and 20. 3. ENLOUTQ = LOW (DLOOP, CLOOP enabled); ENLINQ = LOW (DIN, CIN enabled) and maximum output swing; COUT, COUTQ, DOUT, DOUTQ, POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO, PRSCLOQ, DLOOP, DLOOPQ, CLOOP and CLOOPQ are not connected. 4. The output swing is adjustable in 16 steps controlled by bits RFS in the I2C-bus register IOCNF0 (address CBH). 5. For multiplexing ratio 10:1, the I2C-bus register MUXTIMING (address FDH) should be programmed with 0000.0100 (04H) for supporting 3.2 Gbits/s. The highest supported bit rate for multiplexing ratio 10:1 in a pin programmed application is 2.7 Gbits/s. 6. The output swing is adjustable in 16 steps controlled by bits MFS in the I2C-bus register IOCNF2 (address C8H). 7. Reference frequency of 19.44 MHz, with a phase-noise of less than -140 dBc for frequencies of more than 12 kHz from the carrier. Measured for 60 seconds within the appropriate bandwidth. 8. For bit rates lower than 1.8 Gbits/s, the jitter decreases with the octave division ratio. 2003 May 14 37 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW handbook, full pagewidth MBL556 50 ICCD (mA) 40 LVPECL standard 30 CML AC 20 LVPECL floating 10 CML DC 0 0 5 10 15 value of address C8H, bit 3 to bit 0 Fig.18 Supply current per parallel output. MDB064 handbook, full pagewidth 1000 Vo(p-p) (mV) 800 LVPECL DEFAULT CML 600 400 200 0 0 5 10 15 value of address C8H, bit 3 to bit 0 Fig.19 Output voltage swing of parallel output. 2003 May 14 38 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW handbook, full pagewidth 60 MDB065 50 ICCD (mA) 40 CML AC 30 CML DC 20 10 0 0 5 10 15 value of address CBH, bit 3 to bit 0 Fig.20 Supply current per serial output. handbook, full pagewidth 1100 MDB066 1000 Vo(p-p) (mV) 800 600 400 DEFAULT 200 0 0 5 10 15 value of address CBH, bit 3 to bit 0 Fig.21 Output voltage swing of serial output. 2003 May 14 39 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW handbook, full pagewidth SWING CONTROL VCC Vterm transmission lines 50 2V optional AC coupling OUT Iswing OUTQ 50 to highimpedance input 50 in 50 on-chip off-chip MBL562 Fig.22 Parallel output standard LVPECL mode. handbook, full pagewidth SWING CONTROL VCC OUT transmission lines 50 to highimpedance input Iswing OUTQ 50 100 in on-chip off-chip MBL560 Fig.23 Parallel output floating LVPECL mode (DC-coupled). 2003 May 14 40 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW handbook, full pagewidth SWING CONTROL VCC Vbias AC coupling OUT transmission lines 50 Iswing OUTQ 50 50 50 to highimpedance input in on-chip off-chip MBL561 Fig.24 Parallel output floating LVPECL mode (AC-coupled). handbook, full pagewidth SWING CONTROL VCC Vbias 50 transmission lines 50 to highimpedance input 50 100 100 OUT Iswing OUTQ 50 in on-chip off-chip MDB067 Fig.25 Parallel output CML mode (AC-coupled). 2003 May 14 41 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW handbook, full pagewidth SWING CONTROL VCC 100 100 50 transmission lines 50 50 OUT Iswing OUTQ 50 to highimpedance input in on-chip off-chip MBL564 Fig.26 Parallel output CML mode (DC-coupled). handbook, full pagewidth SWING CONTROL VCC Vbias 50 transmission lines 50 to highimpedance input 50 50 50 OUT Iswing OUTQ 50 in on-chip off-chip MDB068 Fig.27 Serial output CML mode (AC-coupled). 2003 May 14 42 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW handbook, full pagewidth SWING CONTROL VCC 50 50 50 transmission lines 50 50 OUT Iswing OUTQ 50 to highimpedance input in on-chip off-chip MDB069 Fig.28 Serial output CML mode (DC-coupled). handbook, full pagewidth PICLK t h(co) t su(co) D00 to D15, PARITY valid data POCLK MBL581 The timing is measured from the crossover point of the reference signal to the crossover point of the input. Fig.29 Parallel bus co-directional timing. 2003 May 14 43 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter TZA3017HW handbook, full pagewidth D00 to D15, PARITY valid data t su(contra) t h(contra) POCLK MBL582 The timing is measured from the crossover point of the reference signal to the crossover point of the input. Fig.30 Parallel bus contra-directional timing. handbook, full pagewidth COUT, CLOOP t D-C DOUT, DLOOP MBL583 The timing is measured from the crossover point of the reference signal to the crossover point of the output. Fig.31 RF output timing. 2003 May 14 44 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter PACKAGE OUTLINE HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad TZA3017HW SOT638-1 c y exposed die pad side X Dh 75 76 51 50 ZE A e E HE wM bp pin 1 index Lp L detail X Eh A A2 A1 (A3) 100 1 wM ZD 25 bp D HD 26 e vM A B vM B 0 scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 14.1 13.9 Dh 7.1 6.1 E(1) 14.1 13.9 Eh 7.1 6.1 e 0.5 HD 10 mm HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 1.15 0.85 1.15 0.85 7 0 16.15 16.15 15.85 15.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 01-03-30 03-04-07 2003 May 14 45 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. TZA3017HW If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2003 May 14 46 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3) TZA3017HW SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable suitable not not recommended(4)(5) recommended(6) 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2003 May 14 47 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION TZA3017HW This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 May 14 48 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter PURCHASE OF PHILIPS I2C COMPONENTS TZA3017HW Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2003 May 14 49 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter NOTES TZA3017HW 2003 May 14 50 Philips Semiconductors Product specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic transmitter NOTES TZA3017HW 2003 May 14 51 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403510/02/pp52 Date of release: 2003 May 14 Document order number: 9397 750 10574 |
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